This invention relates to a method for manufacturing an integrated circuit (IC) device and more specifically an IC device including an isolated bipolar transistor.
Recently there have been developed semiconductor integrated circuits which enjoy increasingly improved capability of high-speed operation and large scale integration along with the advances in the processing techniques. Essential processes related to the improvement in the operating speed of semiconductor IC's are processes for miniaturization and oxide film isolation which affect reductions in parasitic capacitance and parasitic resistance. In a bipolar transistor, for example, emitterbase junction capacitance, base-collector junction capacitance, collector-substrate junction capacitance, collector series resistance, and base resistance are primary factors which determine the switching speed. High-speed operation necessitates reductions in these factors. Moreover, since the techniques needed for achievement of high-speed operation and large scale integration tend to be complicated, generally requiring an increased number of manufacturing processes, it is important in the aspects of mass production and cost to simplify these individual processes.
A borsenic process utilizing simultaneous diffusion of boron and arsenic ("borsenic") from a doped oxide source is disclosed in IEEE Journal of Solid-State Circuits, Vol. SC-11, No. 4, August, 1976, pp. 495-499. Fabrication of an isolated bipolar transistor in accordance with this borsenic process is advantageous to the simplification of processes and improvement in performance. However, since an SiO.sub.2 layer doped with As.sub.2 O.sub.3 and B.sub.2 O.sub.3 is used as an impurity source for the formation of emitter and internal base regions, it is necessary that, in forming an emitter contact hole by selectively removing the doped SiO.sub.2 layer, a margin with a fixed width for mask alignment be secured around the contact hole. As a result, it becomes difficult to reduce the emitter size. Further, it a PN-junction between the emitter and base is in contact with an oxide island for isolation, the sides of the oxide island will be etched to an unusual degree to expose the PN-junction during the etching step for forming the emitter contact hole, thereby causing a short circuit between the emitter and base. In forming the SiO.sub.2 layer containing As.sub.2 O.sub.3 and B.sub.2 O.sub.3, SiO.sub.2 is doped simultaneously with both these impurities. Accordingly, it is hard to control in a constant manner the concentrations of these two types of impurities in SiO.sub.2 between lots. Therefore, the depths of the internal base and emitter regions will possibly lack in uniformity.